1. Field of the Invention
The present invention is directed in general to the field of data processing systems. In one aspect, the present invention relates to direct memory access management within data processing systems.
2. Description of the Related Art
Data processing systems typically include one or more central processing units (CPU), one or more levels of caches, one or more external memory devices, and input/output (I/O) mechanisms, all interconnected via an interconnection of buses and bridges. In addition to these hardware components, data processing systems also include one or more software (or firmware) components, such as an Operating System (OS) and one or more programs which interact with the OS. To facilitate memory access operations, direct memory access (DMA) operations are used to provide data transfer operations (e.g., from external memory to a local cache memory) without requiring direct processor oversight and control. Typically, a hardware DMA controller is provided for a processor which allows multiple DMA requests to be made on different logical channels. These channels can be used independently to initiate multiple simultaneous asynchronous DMA data transfers. A typical software programming model would consist of initiating and waiting for DMA data requests on specific logical channels that are based on some sort of static mapping of the data to a channel. This results in operations on unrelated data that can potentially map to the same logical channel, resulting in false dependencies, which may in turn result in performance degradation.
Accordingly, there is a need for a system and method for controlling multiple DMA transfer requests to efficiently and quickly allocate DMA channels. There is also a need for a method and system for dynamically allocating logical channels for DMA transfers so as to reduce false dependencies. In addition, there is a need for a system and method to rapidly and efficiently reclaim deallocated DMA channels. Further limitations and disadvantages of conventional DMA allocation solutions will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.